1. Field of the Invention
The present invention relates to a magnetic random access memory, more specifically, for example, to arrangements of drivers and sinkers of a magnetic random access memory, and a decoding system.
2. Description of the Related Art
A magnetic random access memory (MRAM) is a memory device in which “1” or “0” information is stored using a magnetoresistive effect, and a ferromagnetic tunneling junction (MTJ) element is used as a memory cell. The MRAM has nonvolatility, high integrating property, high reliability, low power consumption, and high-speed operation and is one of universal memory device candidates.
At present, information is recorded in the memory cell, when a magnetic field is applied to the MTJ element to change a spin direction of a free layer of the MTJ element. The magnetic field is generated by a current which flows through two write lines (bit line, word line) crossing each other at right angles.
Three factors define a maximum value of a scale of one memory cell array. The three factors are an applied potential difference V between opposite-ends of the write line at a writing time, a write current I, and a resistance R of the write line per memory cell. Specifically, assuming that the number of memory cells controlled by one write line is n, a relation equation V=nRI is obtained by Ohm's law. Moreover, the number n of the memory cells is determined depending on the potential difference V, the write current I, and the resistance R.
It is currently difficult to apply high potentials to the opposite ends of a write wire because large write current, for example several mA to 10 mA, is needed and transistors with high withstanding voltage need to be mounted. Therefore, the number n of the memory cells is limited to be small. As a result, a large memory cell array is difficult to achieve.
Reducing resistance of the write line to enlarge the memory cell array is proposed. However, Much larger memory cell array to achieve high integration is needed.
Jpn. Pat. Appln. KOKAI Publication No. 2004-213771 discloses that the write bit line is connected to the MTJ element to reduce a bit line current.